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microprocessor supervisory circuits adm8690/adm8691/adm8692/adm8693/adm8695 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from it s use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technolo gy way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 - 2011 analog devices, inc. all rights reserved. features upgrade for adm690 to adm695, max690 to max695 specified over temperature low power consumption (0.7 mw) precision voltage monitor reset assertion down to 1 v v cc low switch on resistance 0.7 normal, 7 in backup high current drive (100 ma) wat chdog timer: 100 ms, 1.6 s, or adjustable 400 na standby current automatic battery backup power switching extremely fast gating of chip enable signals (3 ns) voltage monitor for power fail available in tssop package applications microprocessor systems comp uters controllers intelligent instruments automotive systems product highlights the adm8690 and adm8692 are available in 8- lead, pdip packages and provide: 1. power - on reset output during power - up, power - down, and brownout conditions. the reset output remains operational with v cc as low as 1 v. 2. battery backup switching for cmos ram, cmos microprocessor, or other low power logic. 3. a reset pulse if the optional watchdog timer has not been toggled within a specified time. 4. a 1.3 v threshold detect or for power - fail warning, low battery detection, or to monitor a power supply other than 5 v. the adm8691, adm8693, and adm8695 are available in 16 - lead pdip and small outline packages (including tssop) and provide three additional functions: 1. write prote ction of cmos ram or eeprom. 2. adjustable reset and watchdog timeout periods. 3. separate watchdog timeout, backup battery switchover, and low v cc status outputs. functional block dia grams reset 1.3v reset generator 2 watchdog transition detector (1.6s) 4.65v 1 adm8690/ adm8692 watchdog input (wdi) power fail input (pfi) v cc v batt v out power fail output (pfo) 1 voltage detector = 4.65v (adm8690) 4.40v (adm8692) 2 reset pulse width = 50ms (ad8690, adm8692) 00093-001 figure 1 . adm8690/adm8692 1.3v low line reset reset osc in osc sel batt on adm8691/ adm8693/ adm8695 4.65v 1 reset and watchdog time base reset generator watchdog transition detector watchdog timer power fail input (pfi) watchdog input (wdi) ce in v cc v batt v out power fail output (pfo) watchdog output (wdo) ce out 1 voltage detector = 4.65v (adm8691, adm8695) 00093-002 4.40v (adm8693) figure 2 . adm8691/adm8693/adm8695
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 product highlights ........................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 circuit information ........................................................................ 10 battery switchover section ........................................................ 10 power - fail reset output ......................................................... 10 watchdog timer reset ............................................................ 11 watchdog output ( wdo ) ........................................................ 12 ce gating and ram write protection (adm8691/adm8693/adm8695) ......................................... 12 power - fail warning comparator ............................................. 13 application information ................................................................ 14 increasing the drive current .................................................... 14 using a rechargeable battery f or backup ............................... 14 adding hysteresis to the power - fail comparator ................. 14 monitoring the status of the battery ....................................... 14 alternate watchdog input drive circuits ............................... 15 typical applications ....................................................................... 16 adm8690 and adm8692 ......................................................... 16 adm8691, adm8693, and adm8695 ................................... 16 reset output ............................................................................ 16 power - fail detector ................................................................... 17 ram write protection ............................................................... 17 watchdog timer ......................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 19 revision history 6 /11 rev. a to rev. b deleted adm8694 ......................................................... throughout updated figure 11, figure 12, and figure 13 ................................ 9 u pdated outline dimensions ....................................................... 18 9 /06 rev. 0 to rev. a updated format .................................................................. universal changes to absolute maximum ratings ....................................... 6 updated ordering guide ............................................................... 20 2/97 revision 0: initial version
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 3 of 20 general description the adm869 x family of supervisory circuits offers complete single- chip solutions for power supply monitoring and battery control functions in microprocessor systems. these functions include microprocessor reset, backup battery switchover, watchdog timer, cmos ram write protection, and power failure warning. the c omplete family provides a variety of configurations to satisfy most microprocessor system requirements. the adm869 x family is fabricated using an advanced epitaxial cmos process combining low power consumption (0.7 mw), extremely fast chip enable gating (3 ns), and high reliability. reset assertion is guaranteed with v cc as low as 1 v. in addition, the power switching circuitry is designed for minimal voltage drop thereby permitting increased output current drive of up to 100 ma without the need of an external pass transistor. see table 1 for a product selection guide li sting the characteristics of each device in the adm869 x family. to place an order, use the ordering guide provide d as the last section of this data sheet . table 1 . product selection guide part number nominal reset time nominal v cc reset threshold nominal watchdog timeout period battery backup switching base drive ext pnp chip enable signals adm8690 50 ms 4.65 v 1.6 s yes no no adm8691 50 ms or adj 4.65 v 100 ms, 1.6 s, adj yes yes yes adm8692 50 ms 4.4 v 1.6 s yes no no adm8693 50 ms or adj 4.4 v 100 ms, 1.6 s, adj yes yes yes adm8695 200 ms or adj 4.65 v 10 0 ms, 1.6 s, adj yes yes yes
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 4 of 20 specifications v cc = full operating range, v batt = 2.8 v, t a = t min to t max , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments battery backup switching v cc operating voltage range adm8690, adm8691, adm8695 4.75 5.5 v adm8692, adm8693 4.5 5.5 v v bat t operating voltage range adm8690, adm8691, adm8695 2.0 4.25 v adm8692, adm8693 2.0 4.0 v v out output voltage v cc ? 0.005 v cc ? 0.0025 v i out = 1 ma v cc ? 0.2 v cc ? 0.125 v i out 100 ma v out in battery backup mode v bat t ? 0.005 v bat t ? 0.002 v i out = 250 a, v cc < v bat t ? 0.2 v supply current (excludes i out ) 140 200 a i out = 100 a supply current in battery b ackup mode 0.4 1 a v cc = 0 v, v bat t = 2.8 v battery standby current 5.5 v > v cc > v bat t + 0.2 v + = discharge, ? = charge ?0.1 +0.02 a t a = 25c battery switchover threshold 70 mv power -up v cc C v bat t 50 mv power - down battery switchov er hysteresis 20 mv batt on output voltage 0.3 v i sink = 3.2 ma batt on output short - circuit current 55 ma batt on = v out = 4.5 v sink current 0.5 2.5 25 a batt on = 0 v source current reset and watchdog timer reset voltage threshol d adm8690, adm8691, adm8695 4.5 4.65 4.73 v adm8692, adm8693 4.25 4.4 4.48 v reset threshold hysteresis 40 mv reset timeout delay adm8690, adm8691, adm8692, adm8693 , 35 50 70 ms osc sel = high adm8695 140 200 2 80 ms osc sel = high watchdog timeout period, internal oscillator 1.0 1.6 2.25 s long period 70 100 140 ms short period watchdog timeout period, external clock 3840 4064 4097 cycles long period 768 1011 1025 cycles short perio d minimum wdi input pulse width 50 ns v il = 0.4, v ih = 3.5 v reset output voltage @ v cc = 1 v 4 20 mv i sink = 10 a, v cc = 1 v reset , low line output voltage 0.05 0.4 v i sink = 1.6 ma, v cc = 4.25 v 3.5 v i source = 1 a reset , wdo output voltage 0.4 v i sink = 1.6 ma 3.5 v i source = 1 a output short - circuit source current 1 10 25 a output short - circuit sink current 2 5 ma wdi input threshold 1 logic low 0.8 v logic high 3.5 v wdi input current 1 10 a wdi = v out ?10 ?1 a wdi = 0 v
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 5 of 20 parameter min typ max unit test conditions/comments power-fail detector pfi input threshold 1.25 1.3 1.35 v v cc = 5 v pfi input current ?25 0.01 +25 na pfo output voltage 0.4 v i sink = 3.2 ma 3.5 v i source = 1 a pfo short-circuit source current 1 3 25 a pfi = low, pfo = 0 v pfo short-circuit sink current 25 ma pfi = high, pfo = v out chip enable gating ce in threshold 0.8 v v il 3.0 v v ih ce in pull-up current 3 a ce out output voltage 0.4 v i sink = 3.2 ma v out ? 1.5 v i source = 3.0 ma v out ? 0.05 v i source = 1 a, v cc = 0 v ce propagation delay 3 7 ns oscillator osc in input current 2 a osc sel input pull-up current 5 a osc in frequency range 0 500 khz osc sel = 0 v osc in frequency with external capacitor 4 khz osc sel = 0 v, c osc = 47 pf 1 wdi is a three-level input that is internally biased to 38% of v cc and has an input impedance of approximately 5 m.
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 6 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating v cc ?0.3 v to +6 v v bat t ?0.3 v to +6 v all other inputs ?0.3 v to v out + 0.5 v input current v cc 200 ma v bat t 50 ma gnd 20 ma digital output current 20 ma power dissipation, n - 8 pdip 400 mw ja thermal impedance 120 c/w power dissipation, r - 8 soic 400 mw ja thermal impedance 120 c/w power dissipation, n - 16 pdip 600 mw ja thermal impedance 135 c/w power dissipation, ru - 16 tssop 600 mw ja thermal impedance 158 c/w power dissipation, r - 16 soic_n 600 mw ja thermal impedance 110 c/w power dis sipation, rw - 16 soic_w 600 mw ja thermal impedance 73c/w operating temperature range industrial (a version) ?40 c to +85c lead temperature (soldering, 10 sec) 300c storage temperature range ?65 c to +150c stresses above those listed under abs olute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposur e to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 7 of 20 pin configurations and function descript ions 1 2 3 4 8 7 6 5 pfo wdi reset gnd pfi adm8690/ adm8692 top view (not to scale) v out v cc v batt 00093-003 figure 3 . adm8690 and adm8692, pin configuration 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 wdo reset reset gnd pfo wdi batt on low line osc in osc sel pfi adm8691/ adm8693/ adm8695 top view (not to scale) v batt v out v cc ce in ce out 00093-004 figure 4 . adm8691, adm8693, and adm8695 pin configuration table 4 . pin function descriptions mnemonic function v cc power supply input. 5 v nominal. v bat t backup battery input. v out output voltage. v cc or v bat t is inte rnally switched to v out , depending on which is at the highest potential. v out can supply up to 100 ma to power cmos ram. connect v out to v cc if v out and v bat t are not used. gnd ground. this is the 0 v ground reference for all signals. rese t logic output. reset goes low if v cc falls below the reset threshold, or the watchdog timer is not serviced within its timeout period. the reset threshold is typically 4.65 v for the adm8690/adm8691/adm8695 and 4.4 v for the adm8692 a nd adm8693. reset remains low for 50 ms (adm8690/adm8691/adm8692/adm8693) or 200 ms ( adm8695) after v cc returns above the threshold. reset also goes low for 50 ms (adm8690/adm8691/adm8692/adm8693) or 200 ms (adm8695) if the watchdog timer is enabled but not serviced within its timeout period. the reset pulse width can be adjusted on the adm8691/adm8693/adm8695 , as shown in table 5 . the reset output has an in ternal 3 a pull- up, and can either connect to an open collector reset bus or directly drive a cmos gate without an external pull - up resistor. wdi watchdog input. wdi is a three - level input. if wdi remains either high or low for longer than the watchdog timeout period, reset pulses low and wdo goes low. the timer resets with each transition on the wdi line. the watchdog timer can be disabled if wdi is left floating or is driven to midsupply. pfi power - fail input. pfi is the noninverting input to the power - fail comparator . w hen pfi is less than 1.3 v, pfo goes low. connect pfi to gnd or v out when not used. pfo power - fail output. pfo is the output of the power - fail comparator. it goes l ow when pfi is less than 1.3 v. the comparator is turned off and pfo goes low when v cc is below v bat t . ce in logic input. the input to the ce gating circuit. when not in use, connect this pin to gnd or v out . ce out logic output. ce out is a gated version of the ce in signal. ce out tracks ce in when v cc is above the reset threshold. if v cc is below the reset threshold, ce out is forced high. see figure 21 and figure 22 . bat t on logic output. batt on goes high when v out is internally switched to the v bat t input. it goes low when v out is internall y switched to v cc . the output typically sinks 35 ma and can directly drive the base of an external pnp transistor to increase the output current above the 100 ma rating of v out . low line logic output. low line goes low when v cc falls below the reset threshold. it returns high as soon as v cc rises above the reset threshold. reset logic output. reset is an active high output. it is the inverse of reset . osc sel logic oscillator select input. when osc sel is unconnected (floating) or driven high, the internal oscillator sets the reset active time and watchdog timeout period. when osc sel is low, the external oscillator input, osc in, is enabled. osc sel has a 3 a internal pull - up (see table 5 ). osc in oscillator logic input. with osc sel low, osc in can be driven by an external clock signal or an external capacitor can be connected between osc in and gnd. this sets both the reset active pulse timing and the watchdog timeout period (see table 5 and figure 17, figure 18, figure 19 , and figure 20 ). with osc sel high or floating, the inte rnal oscillator is enabled and the reset active time is fixed at 50 ms typical (adm8691/adm8693) or 200 ms typical (adm8695). in this mode , the osc in pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. in both modes, the timeout period immediately after a reset is 1.6 s typical. wdo logic output. the watchdog output, wdo , goes low if wdi remains either high or low for longer than the watchdog timeout period. wdo is set high by the next transition at wdi. if wdi is unconnected or at midsupply, the watchdog timer is disabled and wdo remains high. wdo also goes high when low line goes low.
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 8 of 20 typical performance characteristics 5.00 4.94 4.99 4.98 4.97 4.96 4.95 v out (v) i out (ma) 10 20 30 40 50 60 70 80 90 100 00093-015 figure 5. v out vs. i out normal operation 2.800 2.786 2.798 2.794 2.792 2.790 2.788 2.796 v out (v) i out (a) 150 250 350 450 550 650 750 850 950 1050 00093-016 figure 6. v out vs. i out battery backup 10 90 100 0% a4 3.36v 1v 1v 500ms 00093-017 figure 7 . reset output voltage vs. supply voltage temperature (c) 1.315 1.295 1.280 1.290 1.285 1.310 1.305 1.300 pfi input threshold (v) ?60 ?30 0 30 60 90 120 00093-018 figure 8. p fi input threshold vs. temperature temperature (c) 53 52 49 51 50 reset active time (ms) v cc = 5v adm8690/ adm8691/ adm8692/ adm869 3 20 40 60 80 100 120 00093-019 figure 9 . reset active time vs. temperature 4.69 4.67 4.55 4.65 4.63 reset voltage threshold (v) 4.61 4.59 4.57 temperature (c) v cc = 5v ?60 ?30 0 30 60 90 120 00093-020 figure 10 . reset voltage threshold vs. temperature
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 9 of 20 time ( s) 6 5 0 1.35 1.25 2 1 4 3 v cc = 5v t a = 25c pfo v pfi 1.3v 30pf 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 00093-021 pfi pfo figure 11 . power - fail comparator respon se time falling time ( s) 6 5 0 1.35 1.25 2 1 4 3 0 10 20 30 40 50 60 70 80 pfo pfi pfo v pfi 1.3v 30pf v cc = 5v t a = 25c 90 00093-022 figure 12 . power - fail comparator response time rising time ( s) 6 5 0 1.35 1.25 2 1 4 3 0 0. 2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 pfo 5v v pfi 1.3v 10k? 30pf v cc = 5v t a = 25c 00093-023 pfi pfo figure 13 . power - fail comparator response time with pull - up resistor
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 10 of 20 circuit information battery switchover section the battery switchover circuit compares v cc to the v batt input, and connects v out to whichever is higher. switchover occurs when v cc is 50 mv higher than v batt as v cc falls, and when v cc is 70 mv greater than v batt as v cc rises. this 20 mv of hysteresis prevents repeated rapid switching if v cc falls very slowly or remains nearly equal to the battery voltage. gate drive v cc v batt v out batt on (adm8690, adm8695) 100 mv 700 mv internal shutdown signal when v batt > (v cc + 0.7v) 0 0093-005 figure 14. battery switchover schematic during normal operation, with v cc higher than v batt , v cc is internally switched to v out through an internal pmos tran- sistor switch. this switch has a typical on resistance of 0.7 and can supply up to 100 ma at the v out terminal. v out is normally used to drive a ram memory bank, requiring instantaneous currents of greater than 100 ma. if this is the case, a bypass capacitor should be connected to v out . the capacitor provides the peak current transients to the ram. a capacitance value of 0.1 f or greater can be used. if the continuous output current requirement at v out exceeds 100 ma, or if a lower v cc ? v out voltage differential is desired, an external pnp pass transistor can be connected in parallel with the internal transistor. the batt on output (adm8691/ adm8693/adm8695) can directly drive the base of the external transistor. a 7 mosfet switch connects the v batt input to v out during battery backup. this mosfet has very low input-to-output differential (dropout voltage) at the low current levels required for battery back up of cmos ram or other low power cmos circuitry. the supply current in battery back up is typically 0.4 a. the adm8690/adm8691/adm8695 operate with battery voltages from 2.0 v to 4.25 v, and the adm8692/ adm8693 operate with battery voltages from 2.0 v to 4.0 v. high value capacitors, either standard electrolytic or the farad- size, double-layer capacitors, can also be used for short-term memory backup. a small charging current of typically 10 na (0.1 a maximum) flows out of the v batt terminal. this current is useful for maintaining rechargeable batteries in a fully charged condition. this extends the life of the backup battery by compensating for its self-discharge current. also note that this current poses no problem when lithium batteries are used for backup because the maximum charging current (0.1 a) is safe for even the smallest lithium cells. if the battery switchover section is not used, v batt should be connected to gnd and v out should be connected to v cc . power-fail reset output reset is an active low output that provides a reset signal to the microprocessor whenever v cc is at an invalid level. when v cc falls below the reset threshold, the reset output is forced low. the nominal reset voltage threshold is 4.65 v (adm8690/ adm8691/adm8695) or 4.4 v (adm8692/adm8693). reset low line v1 v2 v2 v1 v cc t 1 t 1 t 1 = reset time v1 = reset voltage threshold low v2 = reset voltage threshold high hysteresis = v2?v1 00093-006 figure 15. power-fail reset timing on power-up, reset remains low for 50 ms (200 ms for adm8695) after v cc rises above the appropriate reset threshold. this allows time for the power supply and microprocessor to stabilize. on power-down, the reset output remains low with v cc as low as 1 v. this ensures that the microprocessor is held in a stable shutdown condition. this reset active time is adjustable on the adm8691/adm8693/ adm8695 by using an external oscillator or by connecting an external capacitor to the osc in pin. refer to table 5 and figure 17, figure 18, figure 19, and figure 20. the guaranteed minimum and maximum thresholds of the adm8690/adm8691/adm8695 are 4.5 v and 4.73 v, and the guaranteed thresholds of the adm8692/adm8693 are 4.25 v and 4.48 v. the adm8690/adm8691/adm8695 are, therefore, compatible with 5 v supplies with a +10%, ?5% tolerance and the adm8692/adm8693 are compatible with 5 v 10% supplies. the reset threshold comparator has approximately 50 mv of hysteresis. the response time of the reset voltage comparator is less than1 s. if glitches are present on the v cc line that could cause spurious reset pulses, v cc should be decoupled close to the device.
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 11 of 20 in addition to reset , the adm8691/adm8693/adm8695 contain an active high reset output. this is the complement of reset and is intended for processors requiring an active high reset signal. watchdog timer reset the watchdog timer circuit monitors the activity of the micro - processor to check that i t is not stalled in an indefinite loop. an output line on the processor is used to toggle the watchdog input (wdi) line. if this line is not toggled within the selected timeout period, a reset pulse is generated. the nominal watchdog time out period is preset at 1.6 seconds on the adm8690 and adm8692 . the adm8691/adm8693/adm8695 can be configured for either a fixed short 100 ms, or a long 1.6 second timeout period, or for an adjustable timeout period. if the short period is selected, some s ystems ar e unable to service the watchdog timer immediately after a reset, so the adm8691/ adm8693/adm8695 automatically select the long timeout period directly after a reset is issued. the watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activity on wdi or by v cc falling below the reset threshold. the normal (short) timeout period becomes effective following the first transition of wdi after reset has gone inactive. the watchdog timeout period rest arts with each transition on the wdi pin. to ensure that the watchdog timer does not time out, either a high - to - low or low - to - high transition on the wdi pin must occur at, or less than, the minimum timeout period. if wdi remains permanently either high or low, reset pulses are issued after each long (1.6 s) timeout period. the watchdog monitor can be deactivated by floating the watchdog input (wdi) or by connecting it to midsupply. wdi wdo reset t 2 t 1 t 1 t 3 t 1 t 1 = reset time t 2 = normal (short) watchdog timeout period t 3 = watchdog timeout period immediately following a reset 00093-007 figure 16 . watchdog timeout period and reset active time table 5 . adm8691, adm8693, adm8695 reset pulse width and watchdog timeout selections watchdog timeout period reset active period osc sel osc in normal immediately after reset adm8691/adm8693 adm8695 low 1 external clock input 1024 clks 4096 clks 512 clks 2048 clks low 1 external capacitor 400 ms c/47 pf 1.6 s c/47 pf 200 ms c/47 pf 520 ms c/47 pf floating or high low 100 ms 1.6 s 50 ms 200 ms floating or high floating or high 1.6 s 1.6 s 50 ms 200 ms 1 with the osc sel pin low, osc in can be driven by an external clock signal, or an external capacitor (c) can be connected between osc in and gnd. the nomin al internal oscillator frequency is 10.24 khz. the nominal oscillator frequenc y with external capacitor is: f osc (hz) = 184,000/c (pf).
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 12 of 20 on the adm8690/adm8692 the watchdog timeout period is fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms. the adm8691/ adm8693 /adm8695 allow these times to be adjusted , as shown in table 5 . figure 17, figure 18, figure 19, and figure 20 show the various oscillator configurations that can be used t o adjust the reset pulse width and watchdog timeout period. the internal oscillator is enabled when osc sel is high or floating. in this mode, osc in selects between the 1.6 second and 100 ms watchdog timeout periods. with osc in connected high or floating , the 1.6 second timeout period is selected; and with it connected low, the 100 ms timeout period is selected. in either case, the timeout period is 1.6 seconds immediately after a reset. this gives the microprocessor time to reinitialize the system. if osc in is low, the 100 ms watchdog period becomes effective after the first transition of wdi. the software should be written such that the input/output port driving wdi is left in its power - up reset state until the initialization routines are completed and the microprocessor is able to toggle wdi at the minimum watchdog timeout period of 70 ms. watchdog output ( wdo ) the watchdog output wdo (adm8691/adm8693/adm8695) provides a status output that goes low if the watchdog tim er times out and remains low until set high by the next transition on the watchdog input. wdo is also set high when v cc goes below the reset threshold. 8 7 osc sel osc in adm8691/ adm8693/ adm8695 clock 0 to 500khz 00093-008 figure 17 . external clock source 8 7 c osc 00093-009 osc sel osc in adm8691/ adm8693/ adm8695 figure 18 . external capacitor nc nc 8 7 00093-010 osc sel osc in adm8691/ adm8693/ adm8695 figure 19 . internal oscillator (1.6 second watchdog) nc 8 7 00093-011 osc sel osc in adm8691/ adm8693/ adm8695 figure 20 . internal oscillator (100 ms watchdog) ce gating and ram write protection (adm8691/adm8693/adm8695) the adm8691/adm8693/adm8695 products include memory protection circuitry that ensures the integrity of data in memory by preventing write operations when v cc is at an invalid level. there are two additional pins ( ce in and ce out ) that can be used to control the chip enable or write inputs of cmos ram. when v cc is present, ce out is a buffered replica of ce in , with a 3 ns propagation delay. when v cc falls below the reset voltage threshold or v batt , an internal gate forces ce out high, independent of ce in . ce out typically drives the ce , cs , or write input of battery backed up cmos ram. this ens ures the integrity of the data in memory by preventing write operations when v cc is at an invalid level. similar protection of eeproms can be achieved using the ce out to drive the store or write inputs. adm8691 adm8693 adm8695 ce out v cc low = 0 v cc ok = 1 ce in 00093-012 figure 21 . chip enable gating reset low line v1 v2 v2 v1 v cc t 1 t 1 t 1 = reset time v1 = reset voltage threshold low v2 = reset voltage threshold high hysteresis = v2?v1 ce in ce out 00093-013 figure 22 . chip enable timing
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 13 of 20 power - fail warning compara tor an additional comparator is provided for early warning of failure in the microprocessor power supply. the power - fail input (pfi) is compared to an internal 1.3 v reference. the power - fail output ( pfo ) goes low when the voltage at pfi is less than 1.3 v. typically, pfi is driven by an external voltage divider that senses either the unre gulated dc input to the system 5 v regulator or the regulated 5 v output. the voltage divider ratio can be chosen such that the voltage at pfi falls below 1.3 v several milliseconds before the 5 v power supply falls below the reset threshold. pfo is normally used to interrupt the micro processor so that data can be stored in ram and the shut - down procedure executed before power is lost. adm869x 1.3v pfo r1 r2 power fail output power fail input input power 00093-014 figure 23 . power - fail comparator table 6 . input and output status in battery backup mode signal stat us v out v out is connected to v bat t via an internal pmos switch. reset logic low. reset logic high. the open - circuit output voltage is equal to v out . low line logic low. bat t on logic high. the open - circuit v oltage is equal to v out . wdi wdi is ignored. it is internally disconnected from the internal pull - up resistor and does not source or sink current as long as its input voltage is between gnd and v out . the input voltage does not affect supply current. wdo logic h igh. the open circuit voltage is equal to v out . pfi the power - fail comparator is turned off and has no effect on the power - fail output. pfo logic low. ce in ce in is ig nored. it is internally disconnected from its internal pull - up and does not source or sink current as long as its input voltage is between gnd and v out . the input voltage does not affect supply current. ce out logic high. the open circui t voltage is equal to v out . osc in osc in is ignored. osc sel osc sel is ignored.
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 14 of 20 application informat ion increasing the drive current if the continuous output current requirements at v out exceed 100 ma, or if a lower v cc C v out voltage different ial is desired, an external pnp pass transistor can be connected in parallel with the internal transistor. the batt on output (adm8691/ adm8693/adm8695) can directly drive the base of the external transistor. pnp transistor 0.1 f 0.1 f battery v batt v cc v out batt on 5v input power 00093-024 adm8691/ adm8693/ adm8695 figure 24 . increasing the drive current using a rechargeable battery for backup if a capacitor or a rechargeable battery is used for backup then the charging resistor should be connected to v out because this eliminates the discharge path that would exist during power - down if the resistor is connected to v cc . adm869x r 0.1 f 0.1 f v batt v cc v out 5v input power rechargeable battery v out ? v ba tt r i = 00093-025 figure 25 . rechargeable battery adding hysteresis to the power - fail comparator for increased noise immunity, hysteresis can be added to the power - fail comparator. because the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the pfo output and the pfi input as shown in figure 26 . when pfo is low, resistor r 3 sinks current from the su mming junction at the pfi pin. when pfo is high, the series combination of r3 and r4 sources current into the pfi summing junction. this results in differing trip levels for the comparator. 5v 0v pfo 0v v l v h v in v h = 1.3v v l = 1.3v assuming r 4 < < r 3 then hysteresis v h ? v l = 5v 1+ r 1 r 2 r 1 r 3 )( + 1+ r 1 r 2 r 1 (5v ? 1.3v) r 3 (1.3v (r 3 + r 4 )) ) ( ? adm869x 1.3v pfi pfo to microprocessor nmi 5v v cc 7v to 15v input power 7805 r 1 r 2 r 3 r 4 00093-026 r 1 r 2 )( figure 26 . adding hy steresis to the power - fail comparator monitoring the statu s of the battery the power - fail comparator can be used to monitor the status of the backup battery instead of the power supply, if desired. this is shown in figure 27 . t he pfi input samples the battery voltage and generates an active low pfo signal when the battery voltage drops below a chosen threshold. it can be necessary to apply a test load to determine the loaded battery voltage. this is done under processor control using ce out . because ce out is forced high during the battery backup mode, the test load is not applied to the battery while it is in use, even if the microprocessor is not powered. adm869x pfi battery 10m ? 10m ? r 1 r 2 5v input power 20k? optional test load low battery signal to microprocessor i/o pin v ba tt v cc ce out ce in pfo 00093-027 from microprocessor i/o pin applies test load to battery figure 27 . monitoring the battery status
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 15 of 20 alternate watchdog i nput drive circuits the watchdog feature can be enabled and disabled under program control by driving wdi with a three - state buffer (see figure 28 ). when three -st ated, the wdi input floats, thereby disabling the watchdog timer. wdi adm869x watchdog strobe control input 00093-028 figure 28 . programming the watchdog input this circuit is not entirely foolproof, and it is possible for a software fault to erroneously three - state the buffer pre venting the adm869x from detecting that the microprocessor is no longer operating correctly. in most cases, a better method is to extend the watchdog period rather than disable the watchdog. this can be done under program control using the circuit shown in figure 29 . when the control input is high, the osc sel pin is low and the watchdog timeout is set by the external capacitor. a 0.01 f capacitor sets a watchdog time - out delay of 100 seconds. when the control input is low, the osc sel pin is driven high, selecting the internal oscillator. the 100 ms or the 1.6 s period is chosen, depending on which diode is used, as shown in figure 29 . with d1 inserted, the internal timeout is set at 100 ms; with d2 inserted, the timeout is set at 1.6 seconds. adm869x osc sel osc in contro l input 1 1 low = interna l timeout high = externa l timeout d1 d2 00093-029 figure 29 . programming the watchdog input
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 16 of 20 typical applications adm8690 and adm8692 figure 30 shows the adm8690/adm8692 in a typical power monitoring, battery backup application. v out powers the cmos ram. under normal operating conditions with v cc present, v out is internally connected to v cc . if a power failure occurs, v cc decays and v out is switched to v batt , thereby maintaining power for the cmos ram. a reset pulse is also generated when v cc falls below 4.65 v for the adm8690 or 4.4 v for the adm8692. reset remains low for 50 ms after v cc returns to 5 v. the watchdog timer input (wdi) monitors an input/output line fr om the microprocessor system. this line must be toggled once every 1.6 seconds to verify correct software execution. failure to toggle the line indicates that the microprocessor system is not correctly executing its program and can be tied up in an endless loop. if this happens, a reset pulse is generated to initialize the microprocessor. if the watchdog timer is not needed, the wdi input should be left floating. the power - fail input, pfi, monitors the input power supply via a resistive divider network. the voltage on the pfi input is compared with a precision 1.3 v internal reference. if the input voltage drops below 1.3 v, a power - fail output ( pfo ) signal is generated. this warns of an impending power failure and can be used to interrupt the processor so that the system can be shut down in an orderly fashion. the resistors in the sensing network are ratioed to give the desired power - fail threshold voltage (v t ). v t = (1.3 r1/r2 ) + 1.3 v r1/r2 = ( v t /1.3) ? 1 + 5v 0.1 f wdi gnd pfi battery r 1 r 2 v ba tt v cc pfo adm8690/ adm8692 cmos ram power power microprocessor system nmi i/o line v out reset reset 00093-030 figure 30 . adm8690/adm8692 typical application circuit a figure 31 shows a similar application, but in this case the pfi input monitors the unregulated input to the 7805 voltage regulator. this gives an earlier warning of an impendin g power failure. it is useful with processors operating at low speeds or where there are a significant number of housekeeping tasks to be completed before the power is lost. + input power v > 8v 0.1 f wdi gnd pfi battery r 1 r 2 v ba tt v cc pfo adm8690/ adm8692 cmos ram power power microprocessor system nmi i/o line v out reset reset 7805 0.1 f 00093-031 5v figure 31 . adm8690/adm8692 typical application circuit b adm8691, adm8693, and adm8695 a typical connection for the adm8691/adm8693/adm8695 is shown in figure 32 . cmos ram is powered from v out . when 5 v power is present, this is routed to v out . if v cc fails, v batt is routed to v out . v out can supply up to 100 ma from v cc , but if more current is required, an external pnp transistor can be added. when v cc is higher than v batt , the batt on output goes low, providing up to 25 ma of base drive for the external transistor. a 0.1 f capacit or is connected to v out to supply the transient currents for cmos ram. when v cc is lower than v batt , an internal 20 ? mosfet connects the backup battery to v out . reset nc a0 to 15 i/o line nmi reset microprocessor system pfi gnd osc in osc sel wdi wdo r 1 r 2 v ba tt v cc adm8691/ adm8693/ adm8695 v out 0.1 f system status indicators batt on 3v battery input power 5v 0.1 f 0.1 f cmos ram address decode low line reset ce out ce in pfo 00093-032 figure 32 . adm8691/adm8693/adm8695 typical application reset output the internal voltage detector monitors v cc and generates a reset output to hold the microprocessor reset line low when v cc is below 4.65 v (4.4 v for adm8693). an internal timer holds reset low for 50 ms (200 ms for the adm8695) after v cc rises above 4.65 v (4.4 v for the adm8693). this prevents repeated toggling of reset , even if the 5 v power drops out and recovers with each power line cycle. the crystal oscillator normally used to g enerate the clock for microprocessors can take several milliseconds to stabilize. because most microprocessors need several clock cycles to reset, reset must be held low until the microprocessor clock oscillator has started. the power - up reset pulse lasts 50 ms
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 17 of 20 (200 ms for the adm8695) to allow for this oscillator start - up time. if a different reset pulse width is required, a capacitor should be connected to osc in, or an external clock can be used. refer to table 5 and figure 17, figure 18, figure 19 , and figure 20 . the manual reset switch and the 0.1 f capacitor connected to th e reset line can be omitted if a manual reset is not needed. an inverted, active high, reset output is also available. power - fail detector the 5 v v cc power line is monitored via a resistive potential divider connected to the power - fail input (pfi). when the voltage at pfi falls below 1.3 v, the power - fail output ( pfo ) drives the processors nmi input low. if, for example, a power - fail threshold of 4.8 v is set with resistor r 1 and resistor r 2 , the microprocessor has the time when v cc fal ls from 4.8 v to 4.65 v to save data into ram. an earlier power - fail warning can be generated if the unregulated dc input to the 5 v regulator is available for monitoring. this allows more time for microprocessor housek eeping tasks to be completed before p ower is lost. ram write protection the adm8691/adm8693/adm8695 ce out line drives the chip select inputs of the cmos ram. ce out follows ce in as long as v cc is above the 4.65 v (4.4 v for the adm8693) res et threshold. if v cc falls below the reset threshold, ce out goes high, independent of the logic level at ce in . this prevents the microprocessor from writing erroneous data into ram during power - up, power - down, brownout s, and momentary power interruptions. watchdog timer the microprocessor drives the watchdog input (wdi) with an input/output line. when osc in and osc sel are unconnected , the microprocessor must toggle the wdi pin once every 1.6 seconds to verify proper s oftware execution. if a hardware or software failure occurs such that wdi is not toggled, the adm8691/adm8693 issues a 50 ms ( 200 ms for the adm8695 ) reset pulse after 1.6 seconds. this typically restarts the micro - processor power - up rout ine. a new reset pulse is issued every 1.6 seconds until wdi is again strobed. if a different watchdog timeout period is required, a capacitor should be connected to osc in or an external clock can be used. r efer to table 5 and figure 17, figure 18, figure 19 , and figure 20. the watchdog output ( wdo ) goes low if the watchdog time r is not serviced within its timeout period. once wdo goes low, it remains low until a transition occurs at wdi. the watchdog timer feature can be disabled by leaving wdi unconnected. the reset outp ut has an internal 3 a pull - up and can either connect to an open collector reset bus or directly drive a cmos gate without an external pull - up resistor.
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 18 of 20 outline dimensions compliant t o jedec s t andards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equi v alents for reference on ly and are not appropri a te for use in design. corner leads m ay be configured as whole or half leads. 070606- a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) sea ting plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0. 1 15 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 33 . 8 - lead plastic dual in - line package [pdip] (n- 8) dimensions show n in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equi v alents for reference on ly and are not appropri a te for use in design. corner leads m ay be configured as whole or half leads. compliant t o jedec s t andards ms-001-ab 073106-b 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0. 1 15 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 16 1 8 9 0.100 (2.54) bsc 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 0.210 (5.33) max sea ting plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) figure 34 . 16 - lead plastic dual in - line package [pdip] (n- 16) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 35 . 8- lead standard small outline package [soic_n] nar row body (r- 8) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 36 . 16 - lead standard small outline package [soic_w] wide body (rw - 16) dimensions shown in millimeters and (inches)
adm8690/adm8691/adm8692/adm8693/adm8695 rev. b | page 19 of 20 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equi v alents for reference on ly and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc sea ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 060606- a 45 figure 37 . 16 - lead standard small outline package [soic_n] narrow body (r- 16) dimensions shown in millimeters and (inches) 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 38 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering gui de model 1 temperature range package description package option adm8690an ?40c to +85c 8- lead plastic dual in - line package [pdip] n- 8 ADM8690ANZ ?40c to +85c 8- lead plastic dual in - line package [pdip] n- 8 adm8690arn ?40c to +85c 8- lead standard small outline package [soic_n] r- 8 adm8690arn - reel ?40c to +85c 8- lead standard small outline package [soic_n] r- 8 adm8690arnz ?40c to +85c 8- lead standard small outline package [soic_n] r- 8 adm8691anz ?40c to +85c 16- lead plastic dual in - line package [pdip] n- 16 adm8691arn ?40c to +85c 16- lead standard sm all outline package [soic_n] r- 16 adm8691arn - reel ?40c to +85c 16- lead standard small outline package [soic_n] r- 16 adm8691arnz ?40c to +85c 16- lead standard small outline package [soic_n] r- 16 adm8691arw ?40c to +85c 16- lead standard small ou tline package [soic_w] rw - 16 adm8691arw - reel ?40c to +85c 16- lead standard small outline package [soic_w] rw - 16 adm8691arwz ?40c to +85c 16- lead standard small outline package [soic_w] rw - 16 adm8691aru ?40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adm8691aru - reel ?40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adm8691aruz ?40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adm8692arnz ?40c to +85c 8- lead standard sm all outline package [soic_n] r-8 adm8693an ?40c to +85c 16- lead plastic dual in - line package [pdip] n- 16 adm8693anz ?40c to +85c 16- lead plastic dual in - line package [pdip] n- 16 adm8693arn ?40c to +85c 16- lead standard small outline package [soic_n] r- 16 adm8693arn - reel ?40c to +85c 16- lead standard small outline package [soic_n] r- 16 adm8693arnz ?40c to +85c 16- lead standard small outline package [soic_n] r- 16 adm8693arw ?40c to +85c 16- lead standard small outline package [soi c_w] rw - 16 adm8693arw - reel ?40c to +85c 16- lead standard small outline package [soic_w] rw - 16 adm8693arwz ?40c to +85c 16- lead standard small outline package [soic_w] rw - 16 adm8693aru - reel ?40c to +85c 16- lead thin shrink small outline pack age [tssop] ru -16 adm8693aruz ?40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 adm8695arw ?40c to +85c 16- lead standard small outline package [soic_w] rw - 16 adm8695arw - reel ?40c to +85c 16- lead standard small outline pa ckage [soic_w] rw - 16 adm8695arwz ?40c to +85c 16- lead standard small outline package [soic_w] rw - 16 1 z = rohs compliant part .
adm8690/adm8691/adm8692/adm8693/adm8695 rev . b | page 20 of 20 notes ? 2006 - 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00093 -0- 6 /11(b)

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